1. Field of the Invention
The present invention relates to wafer processing methods and, more particularly, to efficient and cost effective planarization etch operations for wafers.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform wafer planarization operations. Typically, integrated circuit devices are in the form of multi-level structures. Planarization and recess etch are important processes for the integration of embedded devices which are becoming more common. One of the intermediate steps in integration of embedded devices is to fill a previously etched medium to deep trench (or contact) with polysilicon, and to etch it back down to a certain depth. To insure a uniform fill, an excess layer of polysilicon (up to 3000 A) is deposited above a silicon nitride mask. As a result, the removal of polysilicon fill to a certain depth, has two main steps: planarization and recess etch. The planarization step is removing the excess polysilicon layer down to the mask level, and the recess etch step is removal of deposited polysilicon inside the trenches down to a certain depth. In a typical embedded device integration scheme, there are several recess etch steps. The third recess etch application (usually called Recess 3) is extremely challenging because the desired depth below the mask is very shallow. To ensure a controllable and uniform shallow depth in all trenches (or contacts) across the wafer, a very uniform planarization step is typically utilized. In particular, chemical mechanical planarization (CMP) operations are generally used to planarize polysilicon fillings between recess etch processes. Without planarization, fabrication of further polysilicon layers becomes substantially more difficult due to the variations in the surface topography.
A chemical mechanical planarization (CMP) system as is typically utilized to polish a wafer includes system components for handling and physically polishing the surface of a wafer. Such components can be, for example, an orbital polishing pad, or a linear belt polishing pad. Unfortunately, use of such a system can be extremely problematic. To planarize wafers in between etch operations typically requires transporting wafers from an etch machine to a CMP apparatus. Consequently, time is lost when wafers are being transported between the CMP apparatus and an etch apparatus. In addition, transporting wafers can increase the risk of contamination and may require additional cost and expense to minimize contamination during transport. Moreover, a device to transport the wafer between the CMP apparatus and the etch apparatus may be needed.
Furthermore, utilization of the CMP apparatus can have additional troublesome issues with respect to the wafer processing operations. For example, typical CMP apparatuses may be able to planarize a layer of a wafer by polishing away excess polysilicon, but in this process, endpoint of the polishing (or planarizing) process is typically detected by sensing contact with a different layer of the wafer after the first layer has been polished away. Unfortunately, this method may have difficulty in stopping the planarizing process before a part of the second layer is removed by the polishing. Consequently, this may present problems in multiple etching procedures because a single SiN protective layer is often utilized for all of the etches. In such a circumstance, CMP processes may strip away some or all of the SiN layer before the etching process is completed resulting in inconsistent wafer processing and possibly causing damage to the wafer.
Therefore, there is a need for an apparatus that overcomes the problems of the prior art by having a method of accurately planarizing a wafer in an etching chamber without taking the wafer out of the etching chamber where the extent of wafer polishing may be monitored accurately.